1. Field of the Invention
The present invention relates generally to integrated circuit design and testing, and more specifically to a TAP-based method of extracting shadow scan data without the need to load separate instructions for each multiprocessor core.
2. Description of the Related Art
In the testing of integrated circuits and circuit devices, a number of shadow scan registers are implemented in a multi-threaded, multi-core environment for non-destructive examination of system operating state. In typical test access port (TAP) shadow scan operation, separate instructions are required to obtain shadow scan data from each core.
Shadow scan testing involves the copying of data from a functional register into a shadow scan register. A snap instruction captures the data existing in a designated functional register at the time of snap, and copies the data into a shadow register. The shadow register data is output for examination and verification of the data expected to have been in the functional register at the time of the snap instruction. Shadow scan is typically implemented to allow non-destructive examination of selected system state elements while an application is in flight.
In a typical multi-threaded environment, shadow registers are implemented in scan chain logic of varying length, but shadow registers are not exclusive to or limited to scan chain implementation. Typically, when a Joint Test Action Group (JTAG) test access port (TAP) controller, implemented in the control test unit (CTU), is used to issue a shadow scan instruction, a separate instruction is required for each core, and the decoding of the thread identification is performed in the core. In this manner, the shadow scan instruction is issued through the TAP controller for a specific core (in a multi-core environment), and the thread identification is performed in the core when the instruction is executed.
In light of the foregoing, a method and circuit design is desired to enable a TAP-based method of extracting shadow scan data in a multi-threaded, multi-core environment without the need to load separate instructions for each core.